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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
Features
* 16:1 Multiplexer Up to 2.7Gb/s * Targeted for SONET OC-48 / SDH STM-16 (FEC) Applications * Differential LVPECL Low-Speed Interface
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
* On-Chip PLL-Based Clock Generator * 128-Pin 14x20mm PQFP Package * Single +3.3V Supply
General Description
The VSC8169 is a 16:1 multiplexer with integrated clock generator for use in SONET/SDH systems operating at a standard 2.48832Gb/s data rate or a forward error correction (FEC) data rate up to 2.7Gb/s. The internal clock generator uses a Phase-Locked Loop (PLL) to multiply either a 77.76MHz (up to 84.38MHz-FEC) or a 155.52MHz (up to 168.75MHz -FEC) reference clock in order to provide the 2.48832GHz (up to 2.7GHz FEC) clock for internal logic and output retiming. For use with the VSC9210 FEC Encoder/Decoder chipset running at 2.654208Gb/s, a reference clock of 82.944MHz (serial rate divided by 32) should be used. The 16-bit parallel interface incorporates an on-board FIFO eliminating loop timing design issues by providing a flexible parallel timing architecture. The device operates using a 3.3V power supply, and is packaged in a thermallyenhanced plastic package. The thermal performance of the 128-pin PQFP allows the use of the VSC8169 without a heat sink under most thermal conditions.
VSC8169 Block Diagram
CLK16I+ CLK16ID0+ D0Write Pointer
Input Register
16x5 FIFO
Output Retime
DO+ DO-
D15+ D15REFCLKO+ REFCLKOReset CLK16O+ CLK16OREFCLK+ REFCLKF_FREQSEL
Read Pointer
FIFO Control
CLKO+ CLKOFIFO_WAR
Divide by 16
Divide by 2
2.6GHz PLL
G52230-0, Rev 3.6 01/02/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Preliminary Data Sheet
VSC8169
Functional Description
Low-Speed Interface The Upstream Device should use the CLK16O as the timing source for its final output latch (see Figure 1). The Upstream Device should then generate a CLK16I that is phase aligned with the data. The VSC8169 will latch D[15:0] on the rising edge of CLK16I+. The data must meet setup and hold times with respect to CLK16I (see Table 2). In addition to the CLK16O clock output, there also exists a utility REFCLKO output signal, which is a clock with the same rate as that presented at the REFCLK input. A FIFO exists within the VSC8169 to eliminate difficult system loop timing issues. Once the PLL has locked to the reference clock, RESET must be held low for a minimum of five CLK16 cycles to initialize the FIFO, then RESET should be set high and held constant for continuous FIFO operation. For the transparent mode of operation (no FIFO), simply hold RESET at a constant low state (see Figure 2). The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between CLK16O and CLK16I. Once RESET is asserted and the FIFO initialized, the delay between CLK16O and CLK16I can decrease or increase up to one period of the low-speed clock (6.4ns). Should this delay drift exceed one period, the write pointer and the read pointer could point to the same word in the FIFO, resulting in a loss of transmitted data (a FIFO overflow). In the event of a FIFO overflow, an active low FIFO_WARN signal is asserted (for a minimum of five CLK16I cycles) which can be used to initiate a reset signal from an external controller. The CLK16O output driver is a LVPECL output driver designed to drive a 50 transmission line. The transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by 50 to VCC-2V on each line (see Figure 4). At any time, the equivalent split-end termination technique can be substituted for the traditional 50 to VCC-2V on each line. AC-coupling can be achieved by a number of methods. Figure 5 illustrates an example AC-coupling method for the occasion when the downstream device provides the bias point for AC-coupling. If the downstream device were to have internal termination, the line to line 100 resistor may not be necessary. Figure 1: Low-Speed Systems Interface
CLK16I
Write
16 x 5 FIFO
x16
Upstream Device CLK16O
Read
VSC8169
REFCLK 2.6GHz PLL
Divide by 16
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52230-0, Rev 3.6 01/02/01
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
PLL locked to reference clock.
Minimum 5 CLK16 cycles
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Figure 2: Enabling FIFO Operation
FIFO Mode Operation Transparent Mode Operation
RESET
Holding RESET "low" for a minimum of 5 CLK16 cycles, then setting "high" enables FIFO operation. Holding RESET constantly "low" bypasses the FIFO for transparent mode operation.
Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/VCC
VSC8169
Split-end equivalent termination is ZO to VTERM R1 = 125 R2 = 83, Zo=50, VTERM= VCC-2V
R1
R1
Zo
Zo
R1||R2 = ZO VCCR2 + VEER1 R1+R2 = VTERM
R2
R2
VEE Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/-
VSC8169
ZO
ZO
50 VCC-2V
50
G52230-0, Rev 3.6 01/02/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Preliminary Data Sheet
VSC8169
Figure 5: AC Termination of CLK16O+/-, REFCLKO+/-
VSC8169
Zo Zo 50
100nF
downstream
bias point generated internally
50 100nF VCC-2V
High-Speed Data and Clock Output The high-speed data and clock output drivers consist of a differential pair designed to drive a 50 transmission line. The transmission line should be terminated with a 100 resistor at the load between true and complement outputs (see Figure 6). Connection to a termination voltage is not required. The output driver is back terminated to 50 on-chip, providing a snubbing of any reflections. If used single-ended, the high-speed output driver must still be terminated differentially at the load with a 100 resistor between true and complement outputs. The high-speed clock output can be powered down for additional power savings. To power down the highspeed clock, tie the associated pins to VCC (see Table 3, Package Pin Identifications, pins 5,6,7). Figure 6: High-Speed Output Termination
VCC
50
50 100
Pre-Driver
Z0 = 50
VEE
Clock Generator An on-chip PLL generates the 2.48832GHz (or up to 2.7GHz for FEC) transmit clock from the externally provided REFCLK input. The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip loop filter. The loop bandwidth of the PLL is within the SONET specified limit of 2MHz.
Page 4
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52230-0, Rev 3.6 01/02/01
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
The customer can select to provide either a 77.76MHz (up to 84.38MHz- FEC) reference (recommended), or the 2x of that reference, 155.52MHz (up to 168.75MHz-FEC). REF_FREQSEL is used to select the desired reference frequency. REF_FREQSEL = "0" designates REFCLK input as 77.76MHz (up to 84.38MHz-FEC), REF_FREQSEL = "1" designates REFCLK input as 155.52MHz (up to 168.75MHz - FEC) . For use with the VSC9210 FEC Encoder/Decoder chipset running at 2.654208Gb/s, REF_FREQSEL = "0" should be selected with the REFCLK input as 82.944MHz (serial rate divided by 32). The REFCLK should be of high quality since noise on the REFCLK below the loop band width of the PLL will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a VCXO may be required to avoid passing REFCLK noise with greater than 4ps RMS of jitter to the output. The VSC8169 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8169 itself during such conditions.
Low-Speed Inputs The incoming low-speed data and reference clock input are received by LVPECL inputs D[15:0] and REFCLK. Off-chip termination of these inputs is required. For AC-coupling, a bias voltage suitable for AC-coupling needs to be provided. See Figure 7 for external biasing resistor scheme.. In most situations these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. All serial data inputs have the same circuit topology, as shown in Figure 7. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this common mode reference voltage (VCMI) and not exceed the maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage. The external reference should have a nominal value equivalent to the common mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate. Figure 7: AC Termination of Low-Speed LVPECL REFCLK, D[15:0] Inputs Chip Boundary
VCC = 3.3V
Split-end equivalent termination is ZO to VTERM R1 = 83 R2 = 125, Zo=50, VTERM = VCC-2V R1||R2 = ZO VCCR2 + VEER1 = VTerm
VCC
R1 ZO CIN R2
R1+R2
VEE VCC
R1 ZO CIN R2
VEE
VEE = 0V
CIN TYP = 100nF for AC operation
G52230-0, Rev 3.6 01/02/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Preliminary Data Sheet
VSC8169
Supplies The VSC8169 is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to use the device in an ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be -3.3V. If used with VEE tied to -3.3V, the TTL control signals are still referenced to VEE. Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is recommended that the VCC power supply be decoupled using a 0.1F and 0.01F capacitor placed in parallel on each VCC power supply pin as close to the package as possible. If room permits, a 0.001F capacitor should also be placed in parallel with the 0.1F and 0.01F capacitors mentioned above. Recommended capacitors are low-inductance ceramic SMT X7R devices. For the 0.1F capacitor, a 0603 package should be used. The 0.01F and 0.001F capacitors can be either 0603 or 0402 packages. Extra care needs to be taken when decoupling the analog power supply pins (labeled VCCANA). In order to maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8169, the analog power supply pins should be filtered from the main power supply with a 10H C-L-C pi filter. If preferred, a ferrite bead may be used to provide the isolation. The 0.1F and 0.01F decoupling capacitors are still required and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead). For low frequency decoupling, 47F tantalum low inductance SMT caps are sprinkled over the board's main +3.3V power supply and placed close to the C-L-C pi filter. If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling VCC must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V. Figure 8: PLL Power Supply Decoupling Scheme
10 H VCC 10 F 0.1 F 0.1 F 0.01 F VCC_ANA
VEE
VEE_ANA
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52230-0, Rev 3.6 01/02/01
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
AC Characteristics
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Figure 9: Parallel Input Data and Clock Timing Waveform
CLK16PER CLK16I+ Parallel Data Clock Input tDSU TXIN[0:15]+, TXPRTYIN Parallel Data Inputs tDH Valid Data 2
Valid Data 1
CLK16O+ Parallel Data Clock Output = don't care
Figure 10: Serial Data and Clock Output Phase Timing Waveform
CLKOPER
DO+ Differential Serial Data Output
D15 MSB
D14
D13
D1
D0 LSB
Time tSET CLKO+ Differential Clock Output tHOLD
NOTE: Bit 15 (MSB) is received first, Bit 0 (LSB) is received last.
G52230-0, Rev 3.6 01/02/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Table 1: AC Characteristics Parameters
tDSU tDH tDOR,tDOF tCLKR, tCLKF CLK16OD CLKID RCKD CLKOD CLKOPER CLK16OPER tSET tHOLD
Preliminary Data Sheet
VSC8169
Min
0.75 1.0 -- -- 40 30 40 40 -- -- -- --
Description
Data setup time to the rising edge of CLK16I+ Data hold time after the rising edge of CLK16+ DO rise and fall time CLK16O rise and fall times CLK16O duty cycle CLK16I duty cycle Reference Clock duty cycle CLKO duty cycle CLKO period CLK16O period DO setup time with respect to rising CLKO edge DO hold time with respect to rising CLKO edge
Typ
-- -- -- -- -- -- -- -- 401.9 6.4 90 310
Max
-- -- 120 250 60 70 60 60 -- -- -- --
Units
ns ns ps ps % % % % ps ns ps ps
Conditions
20% to 80% into 100 load See Figure 6 See Figures 3 and 4 Assuming 10% distortion of CLKO
SONET-based 77.76MHz or 155.52MHz reference clock SONET-based 77.76MHz or 155.52MHz reference clock Inverting CLKO will switch (approx) tSET and tHOLD values. Inverting CLKO will switch (approx) tset and thold values.
Clock Multiplier Performance
TDJ Output data jitter -- -- 4 ps rms, tested to SONET specification (12kHz to 20MHz) with 2ps rms jitter on REFCLK. rms, tested to SONET specification (12kHz to 20MHz) with 2ps rms jitter on REFCLK. Exceeds SONET/SDH mask
TCJ Jittertol
Output clock jitter Jitter tolerance Tuning Range
-- -- -100
-- --
4 -- +100
ps -- ppm
Figure 11: Differential and Single-Ended Input/Output Voltage Measurement
b
a
Single Ended Swing
=
b
a
Differential Swing
=
* Differential swing () is specified as | b - a | ( or | a - b | ), as is the single-ended swing. Differential swing is specified as equal in magnitude to single-ended swing.
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52230-0, Rev 3.6 01/02/01
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
Table 2: DC Characteristics (Over recommended operating conditions). Parameters
VOH(DO) VOL(DO) VOD(DO) VOCLK(CLKO) VCMO RDO VOH VOL VIH VIL IIH IIL Ri VI VCMI VOH VOL VIH VIL IIH IIL VCC PD ICC
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Description
Output HIGH voltage (DO) Output LOW voltage (DO) Data output differential voltage (DO) CLK output differential voltage (CLKO) Output common-mode voltage Back termination impedance Output HIGH voltage (CLK16O, REFCLKO) Output LOW voltage (CLK16O, REFCLKO) Input HIGH voltage (LVPECL) Input LOW voltage (LVPECL) Input HIGH current (LVPECL) Input LOW current (LVPECL) Input resistance (LVPECL) Input differential voltage (LVPECL) Input common-mode voltage (LVPECL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH Current (TTL) Input LOW Current (TTL) Supply voltage Power dissipation Supply current
Min
VCC0.825 VCC1.30 550 500 2.10 40 VCC1.020 VCC2.000 VCC1.100 VCC2.0 -- -50 10k 200 VCC1.5 2.4 2.0 0.0 -- -- 3.14 -- --
Typ
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.2 350
Max
VCC VCC0.50 900 900 3.00 60 VCC0.700 VCC1.620 VCC0.700 VCC1.540 200 -- -- -- VCC0.5 -- 0.5 5.5 0.8 500 -500 3.47 1.7 490
Units
V V mV mV V V V V V A A mV V V V V V A A V W mA
Conditions
See Figure 12 See Figure 12 100 termination between DO at load 100 termination between DO at load Guaranteed, but not tested See Figure 12 See Figure 12
VIN=VIH(max) VIN=VIL(min)
IOH = -1.0 mA IOL = +1.0 mA
VIN = 2.4V VIN = 0.4V 3.3V 5% Outputs open, VCC = VCC max Outputs open, VCC = VCC max
G52230-0, Rev 3.6 01/02/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Preliminary Data Sheet
VSC8169
Parametric Test Load Circuit
80% 20%
Figure 12: Parametric Measurement Information PECL Rise and Fall Time
Serial Output Load
Z0 = 50
50 VCC-2V
Tr
Tf
Parametric Test Load Circuit High-Speed Data Output
Z0 = 50
50
VCC
Absolute Maximum Ratings (1)
Power Supply Voltage, (VCC)..........................................................................................................-0.5V to +3.8V DC Input Voltage (Differential inputs)....................................................................................-0.5V to VCC +0.5V DC Input Voltage (TTL inputs) .......................................................................................................-0.5V to +5.5V DC Output Voltage (TTL Outputs).........................................................................................-0.5V to VCC + 0.5V Output Current (TTL Outputs) ................................................................................................................... 50mA Output Current (Differential Outputs)......................................................................................................... 50mA Case Temperature Under Bias ...................................................................................................... -55oC to +125oC
NOTE: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
Recommended Operating Conditions
Power Supply Voltage, (VCC).................................................................................................................+3.3V+5% Operating Temperature Range ........................................................... 0oC Ambient to +85oC Case Temperature
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC8169 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V.
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52230-0, Rev 3.6 01/02/01
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
Package Pin Descriptions
Figure 13: Pin Diagram
Top View--128-Pin PQFP
REFCLKO+ REFCLKO- VCC_ANA VEE_ANA REFCLK+ REFCLK-
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
D15+
D14+
D15-
D14- 105
VCC
VCC
VCC
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
104
103
VCC
VEE
VEE
VEE
VEE
NC
NC
NC
NC
NC
NC
NC
NC
NC NC NC VCC VEEP_CLK VEEP_CLK VEEP_CLK VCC CLKO+ CLKOVCC VCC NC NC VEE VEE VEE VCC DO+ DO- VCC NC VCC VCC VCC VEE VEE VEE VEE VEE NC NC NC NC NC NC NC REF_FREQSEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
102 101 100 99 98
VCC D13+ D13- VCC D12+ D12- VEE D11+ D11- VCC D10+ D10- VCC D9+ D9- VEE D8+ D8- VCC D7+ D7- VCC D6+ D6- VEE D5+ D5- VCC D4+ D4- VCC D3+ D3- VEE D2+ D2- VCC NC
VSC8169
97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VEE
VEE
VEE
CLK16O-
CLKI-
VEE
D0-
VCC
FIFO_WARN
VCC
RESET
VCC
CLK16O+
VCC
CLKI+
D0+
VCC
D1-
NC
NC
NC
NC
NC
D1+
NC
G52230-0, Rev 3.6 01/02/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
VCC
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Table 3: Package Pin Identification Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Preliminary Data Sheet
VSC8169
Level
-- -- -- +3.3V GND GND GND +3.3V HS HS +3.3V +3.3V -- -- GND GND GND +3.3V HS HS +3.3V -- +3.3V +3.3V +3.3V GND GND GND GND GND -- -- -- --
Name
NC NC NC VCC VEEP_CLK VEEP_CLK VEEP_CLK VCC CLKO+ CLKOVCC VCC NC NC VEE VEE VEE VCC DO+ DOVCC NC VCC VCC VCC VEE VEE VEE VEE VEE NC NC NC NC
I/O
-- -- -- -- -- -- -- -- O O -- -- -- -- -- -- -- -- O O -- -- -- -- -- -- -- -- -- -- -- -- -- --
Description
No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) Positive power supply High-speed clock VEE power supply (tie to VCC for power down) High-speed clock VEE power supply (tie to VCC for power down) High-speed clock VEE power supply (tie to V CC for power down) Positive power supply High-speed clock output, true High-speed clock output, complement Positive power supply Positive power supply No connect, leave unconnected(1) No connect, leave unconnected(1) Negative power supply Negative power supply Negative power supply Positive power supply High-speed data output, true High-speed data output, complement Positive power supply No connect, leave unconnected(1) Positive power supply Positive power supply Positive power supply Negative power supply Negative power supply Negative power supply Negative power supply Negative power supply No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1)
Page 12
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52230-0, Rev 3.6 01/02/01
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
Pin #
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Level
-- -- -- TTL +3.3V GND TTL GND +3.3V TTL -- -- -- -- -- +3.3V GND LVPECL LVPECL +3.3V LVPECL LVPECL GND LVPECL LVPECL +3.3V LVPECL LVPECL -- +3.3V -- +3.3V LVPECL LVPECL
Name
NC NC NC REF_FREQSEL VCC VEE
FIFO_WARN
I/O
-- -- -- I -- -- O -- -- I -- -- -- -- -- -- -- O O -- I I -- I I -- I I -- -- -- -- I I
Description
No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) Reference clock input select Positive power supply Negative power supply FIFO overflow warning Negative power supply Positive power supply Reset to align FIFO Write and Read pointers No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) Positive power supply Negative power supply Low-speed clock output, true. A divide-by-16 version of the PLL clock. Low-speed clock output, complement. A divide-by-16 version of the PLL clock. Positive power supply Low-speed clock input for latching low-speed data, true Low-speed clock input for latching low-speed data, complement Negative power supply Low-speed differential parallel data Low-speed differential parallel data Positive power supply Low-speed differential parallel data Low-speed differential parallel data No connect, leave unconnected(1) Positive power supply No connect, leave unconnected(1) Positive power supply Low-speed differential parallel data Low-speed differential parallel data
VEE VCC RESET NC NC NC NC NC VCC VEE CLK16O+ CLK16OVCC CLKI+ CLKIVEE D0D0+ VCC D1D1+ NC VCC NC VCC D2D2+
G52230-0, Rev 3.6 01/02/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Preliminary Data Sheet
VSC8169
Level
GND LVPECL LVPECL +3.3V LVPECL LVPECL +3.3V LVPECL LVPECL GND LVPECL LVPECL +3.3V. LVPECL LVPECL +3.3V. LVPECL LVPECL GND LVPECL LVPECL +3.3V. LVPECL LVPECL +3.3V LVPECL LVPECL GND LVPECL LVPECL +3.3V LVPECL LVPECL +3.3V. +3.3V Negative power supply Low-speed differential parallel data Low-speed differential parallel data Positive power supply Low-speed differential parallel data Low-speed differential parallel data Positive power supply Low-speed differential parallel data Low-speed differential parallel data Negative power supply Low-speed differential parallel data Low-speed differential parallel data Positive power supply Low-speed differential parallel data Low-speed differential parallel data Positive power supply Low-speed differential parallel data Low-speed differential parallel data Negative power supply Low-speed differential parallel data Low-speed differential parallel data Positive power supply Low-speed differential parallel data Low-speed differential parallel data Positive power supply Low-speed differential parallel data Low-speed differential parallel data Negative power supply Low-speed differential parallel data Low-speed differential parallel data Positive power supply Low-speed differential parallel data Low-speed differential parallel data Positive power supply Positive power supply
Pin #
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
Name
VEE D3D3+ VCC D4D4+ VCC D5D5+ VEE D6D6+ VCC D7D7+ VCC D8D8+ VEE D9D9+ VCC D10D10+ VCC D11D11+ VEE D12D12+ VCC D13D13+ VCC VCC
I/O
-- I I -- I I -- I I -- I I -- I I -- I I -- I I -- I I -- I I -- I I -- I I -- --
Description
Page 14
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52230-0, Rev 3.6 01/02/01
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
Pin #
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Level
-- LVPECL LVPECL +3.3V LVPECL LVPECL GND -- -- -- -- -- LVPECL LVPECL +3.3V GND LVPECL LVPECL GND +3.3V -- -- GND GND +3.3V.
Name
NC D14D14+ VCC D15D15+ VEE NC NC NC NC NC REFCLK+ REFCLKVCC VEE REFCLKO+ REFCLKOVEE_ANA VCC_ANA NC NC VEE VEE VCC
I/O
-- I I -- I I -- -- -- -- -- -- I I -- -- O O -- -- -- -- -- -- --
Description
No connect, leave unconnected(1) Low-speed differential parallel data Low-speed differential parallel data Positive power supply Low-speed differential parallel data Low-speed differential parallel data Negative power supply No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) Reference clock input, true Reference clock input, complement Positive power supply Negative power supply Reference clock output, true Reference clock output, complement Negative power supply pins for analog parts of CMU Positive power supply pins for analog parts of CMU No connect, leave unconnected(1) No connect, leave unconnected(1) Negative power supply Negative power supply Positive power supply
NOTE: (1) No connect (NC) pins must be left unconnected, or floating. Connecting any of these pins to either the positive or negative power supply rails may cause improper operation or failure of the device; or in extreme cases, cause permanent damage to the device.
G52230-0, Rev 3.6 01/02/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 15
VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Preliminary Data Sheet
VSC8169
Package Information
128-Pin PQFP Package Drawing
PIN 128 PIN 1 PIN 102
Key
RAD. 2.92 .50 (2)
mm
2.35 0.25 2.00 17.20 14.00 23.20 20.00 .88 .50 .22 0-7 .30 .20
Tolerance
MAX MAX +.10 .20 .10 .20 .10 +.15/-.10 BASIC .05 TYP TYP
A A1 A2
E1 E
D D1 E E1 L e b
EXPOSED INTRUSION 0.127 MAX. EXPOSED HEATSINK
2.54 .50
PIN 38 D1 D TOP VIEW 10 TYP.
PIN 64
R R1
A2
A
A1 10 TYP.
e
R
R1
1
STANDOFF
A
Notes: 1) 2) 3) Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package.
.25
A1
0.17
MAX.
b
LEAD COPLANARITY
NOTES: Package #: 101-322-5 Issue #: 2
L
Page 16
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52230-0, Rev 3.6 01/02/01
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
Thermal Considerations
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in the Table 4.
Table 4: Thermal Resistance Symbol
JC CA
Description
Thermal resistance from junction-to-case. Thermal resistance from case-to-ambient with no airflow, including conduction through the leads.
C/W 1.34 25.0
Thermal Resistance with Airflow
Shown in the Table 5 is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst case power of the device multiplied by the thermal resistance.
Table 5: Thermal Resistance with Airflow Airflow
100 lfpm 200 lfpm 400 lfpm 600 lfpm
ca (oC/W)
21 18 16 14.5
Maximum Ambient Temperature without Heatsink
The worst-case ambient temperature without use of a heatsink is given by the equation:
T A ( MAX ) = T C ( MAX ) - P ( MAX ) CA
where:
CA A(MAX) C(MAX) P(MAX)
Theta case-to-ambient at appropriate airflow Ambient air temperature Case temperature (85oC for VSC8169) Power (1.7 W for VSC8169)
G52230-0, Rev 3.6 01/02/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 17
VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
The results of this calculation are listed below:
Table 6: Maximum Ambient Air Temperature without Heatsink Airflow
None 100 lfpm 200 lfpm 400 lfpm 600 lfpm
Preliminary Data Sheet
VSC8169
Max Ambient Tempeature (oC)
43 49 54 58 60
Note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow.
Ordering Information
The order number for this product is formed by a combination of the device number, and package type.
VSC8169
Device Type OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
xx
Package QR: 128PQFP, 14x20mm Body
otice
itesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. This document contains pre-production nformation about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of eatures, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this ocument shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or ill be suitable for or will accomplish any particular task. itesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without writen consent is prohibited.
Page 18
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52230-0, Rev 3.6 01/02/01

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